๐ก
Register
<Cache (L1<L2<L3)
<Main Memory (DRAM)
<Disk (SSD/HDD)
<Network/Cloud
๊ฐ์๋ฉ๋ชจ๋ฆฌ๋ ๋์คํฌ์์ ๋ฉ๋ชจ๋ฆฌ๋ก ์ด๋ป๊ฒ ๊ฐ์ ธ์ฌ ๊ฒ? (์ด์์ฒด์ )
๋ฉ๋ชจ๋ฆฌ์์ ์บ์๋ก ์ด๋ป๊ฒ ๊ฐ์ ธ์ฌ ๊ฒ? (์ปดํจํฐ๊ตฌ์กฐ)
๐ก ์ต๊ทผ ์์ฃผ ์ฌ์ฉ๋๋ ๊ฒ๋ค์ ๋ค์ ์ฌ์ฉ๋ ๊ฐ๋ฅ์ฑ์ด ์๋ค.
โ๏ธ Spatial Locality: nearby references are likely to occur soon
โ๏ธ Temporal Locality : the same references is likely to occur soon
โ๏ธ Speed vs. Size tradeoff
๐ก A small but fast memory located between processor and main memory
โ๏ธ Benefits
โ๏ธ Cache Block Allocation (when to place)
โ๏ธ Cache Block Placement (where to place)
โ๏ธ Cache Block Replacement
Random
LRU (least recently used)
Replacement policy critical for small caches
โ๏ธ Cold-start misses (or compulsory misses)
โ๏ธ Capacity misses
โ๏ธ Conflict misses (or collision misses)
โ๏ธ Invalidation misses (or sharing misses)
[KUOCW] ์ต๋ฆฐ ๊ต์๋์ ์ด์์ฒด์ ๊ฐ์๋ฅผ ์๊ฐํ๊ณ ์ ๋ฆฌํ ๋ด์ฉ์ ๋๋ค. ์๋ชป๋ ๋ด์ฉ์ด ์๋ค๋ฉด ๋๊ธ๋ก ์๋ ค์ฃผ์๋ฉด ๊ฐ์ฌํ๊ฒ ์ต๋๋ค ๐